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L9347
INTELLIGENT QUAD (2X5A/2X2.5A) LOW-SIDE SWITCH
s s s s s s s s s s s s s s s s s s s
Quad low-side switch 2 x 5A designed as conventional switch 2 x 2.5A designed as switched current-regulator Low ON-resistance 2 x 0.2, 2 x 0.35 (typ.) Power SO-36 - package with integrated cooling area Integrated free-wheeling and clamping Z-diodes Output slope control Short circuit protection Selective overtemperature shutdown Open load detection Ground and supply loss detection External clock control Recirculation control Regulator drift detection Regulator error control Regulator resolution 5mA Status monitoring Status push-pull stages Electrostatic discharge (ESD) protection
PowerSO-36 BARE DIE ORDERING NUMBERS: L9347PD L9347DIE1
DESCRIPTION The L9347 is an integrated quad low-side power switch to drive inductive loads like valves used in ABS systems. Two of the four channels are current regulators with current range from 250mA to 2.25A and an accuracy of 10%. All channels are protected against fail functions. They are monitored by a status output.
Figure 1. Pin Connection
GND PGND3 PGND3 Q3 Q3 D3 D3 Q1 Q1 Q2 Q2 D4 D4 Q4 Q4 PGND4 PGND4 N.C.
99AT0060
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
CLK ST3 IN1 IN3 ST1 PGND1 PGND1 VS PGND2 PGND2 TEST EN ST2 IN4 IN2 ST4 VDD VCC
June 2002
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Figure 2. Block Diagram
VS VCC VDD
Internal Supply
EN Overtemperature Channel 4 CLK Open Load IN1 LOGIC Overload Q1 Overtemperature Channel 1
ST1 GND-det. Open Load
IPD
D4 IN4 LOGIC & DA Overload Q4
ST4 GND-det. Overtemperature Channel 3 Overtemperature Channel 2 Open Load IN2 LOGIC Overload
IPD
Q2
ST2 GND-det. Open Load
IPD
D3 IN3 LOGIC & DA Overload Q3
ST3 GND-det. drift-det. TEST
IPD
99AT0059
GND
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PIN DESCRIPTION
N 1 2, 3 4, 5 6, 7 8, 9 10, 11 12, 13 14, 15 16, 17 18 19 20 21 22 23 24 25 26 27, 28 29 30, 31 32 33 34 35 36 Pin GND PGND 3 Q3 D3 Q1 Q2 D4 Q4 PGND 4 NC VCC VDD ST 4 IN 2 IN 4 ST 2 EN TEST PGND 2 VS PGND 1 ST 1 IN 3 IN 1 ST 3 CLK Logic Ground Power Ground Channel 3 Power Output Channel 3 Free-Wheeling Diode Channel 3 Power Output Channel 1 Power Output Channel 2 Free-Wheeling Diode Channel 4 Power Output Channel 4 Power Ground Channel 4 Not Connected 5V Supply 5V Supply Status Output Channel 4 Control Input Channel 2 Control Input Channel 4 Status Output Channel 2 Enable Input for all four Channels Enable Input for Drift detection Power Ground Channel 2 Supply Voltage Power Ground Channel 1 Status Output Channel 1 Control Input Channel 3 Control Input Channel 1 Status Output Channel 3 Clock Input Function
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ABSOLUTE MAXIMUM RATINGS The absolute maximum ratings are the limiting values for this device. Damage may occur if this device is subjected to conditions which are beyond these values.
Symbol EQ Parameter Switch off energy for inductive loads Supply voltage Supply voltage Output voltage static Output voltage during clamping Input voltage IN1 to IN4, EN Input Voltage CLK Output voltage status Recirculation circuits D3, D4 max. reverse breakdown voltage of free wheeling diodes D3, D4 Output current for Q1 and Q2 Output current for Q3 and Q4 Output current at reversal supply for Q1 and Q2 Output current at reversal supply for Q3 and Q4 Output current status pin Electrostatical Discharging Output Pins (Qx, Dx) MIL883C vs. Common GND (PGND1-4 + GND) >5 >3 -4 -2 -5 2 4 5 t < 1ms II < |10|mA -1.5 -1.5 -0.3 -0.3 -0.3 Test Conditions Min Typ Max 50 40 6 40 60 6 6 6 40 55 Unit mJ V V V V V V V V V
Voltages
VS VCC, VDD VQ VQ VIN, VEN VCLK VST VD VDRmax
Currents
IQ1/2 IQ3/4 IQ1/2, IPGND1/2 IQ3/4, IPGND3/4 IST ESD ESD internal limited internal limited A A A A mA kV kV
ESD Protection
THERMAL DATA
Symbol Tj Tjc Tstg Tth Thy RthJC Parameter Junction temperature Junction temperature during clamping (life time) Storage temperature Overtemperature shutdown threshold Overtemperature shutdown hysteresis Thermal resistance junction to case Tj Test Conditions Min -40 Typ Max 150 175 190 -55 175 10 2 150 200 Unit C C C C C K/W
t = 30min t = 15min
Tstg
(1) (1)
RthJC
(1) This parameter will not be tested but assured by design.
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OPERATING RANGE
Symbol VS VCC, VDD dVS/dt VQ VQ Supply voltage Supply voltage Supply voltage transient time Output voltage static Output voltage induced by inductive switching Voltage will be limited by internal Z-diode clamping -0.3 -1 -40 Parameter Test Conditions Min. 4.8 4.5 -1 -0.3 Typ. Max. 18 5.5 1 40 60 Unit V V V/s V V
VST IST Tj Tjc
Output voltage status Output current status Junction temperature Junction temperature during clamping
6 1 150 175 190
V mA C C
= 30min = 15min
. ELECTRICAL CHARACTERISTCS: (Vs = 4.8 to 18V; Tj = -40 to 150C unless otherwise specified)
Symbol Power Supply ISON ISOFF Icc Idd Idd Supply current Quiescent current Supply current VCC (analog supply) Supply current VDD (digital supply) Supply current VDD (digital supply) VS 18V (outputs ON) VS 18V (outputs OFF) VCC =5V VDD =5V fCLK=0Hz VDD =5V fCLK=250kHz 5 5 5 5 5 mA mA mA uA mA Parameter Test Condition Min. Typ. Max. Unit
General Diagnostic Functions VQU VthGND VthPGL fCLK,min
ow
Open load voltage Signal-GND-loss threshold Power-GND-loss threshold Clock frequency error
VS 6.5V (outputs OFF) VCC= 5V VCC= 5V
0.3 0.1 1.5 10
0.33
0.36 1
x VQ V V kHz % %
2.5
3.5 100
DCCLKe_l Clock duty cycle error detection low DCCLKe_ Clock duty cycle error detection high
high
fCLK= 250 kHz fCLK= 250 kHz VCC = VDD = 5V 55 2
33,3 66,6
45
VSloss
Supply detection
4.5
V
Additional Diagnostic Functions channel 1 and channel 2 (non regulated channels) IQU1,2 IQO1,2 Open-load current channel 1, 2 Over-load current channel 1, 2 VS 6.5V VS 6.5V 50 5 7.5 140 9 mA A
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ELECTRICAL CHARACTERISTCS: (continued) (Vs = 4.8 to 18V; Tj = -40 to 150C unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit
Additional Diagnostic Functions channel 3 and channel 4 (regulated channels) DCOUT IQO3,4 Vrerr Output duty cycle range Overload current channel 3,4 Recirculation error shutdown threshold (open D3/D4) filtered with 10ms VS 6.5V Iout > 50mA VIN3 = VIN4 = PWMIN VTEST = H 10 2.5 45 -14.3 5 50 90 8 60 +14.3 % A V %
PWMdOU Output PWM ratio during drift T comparison
Digital Inputs (IN1 to IN4, ENA, CLK, TEST). The valid PWM-Ratio for IN3/IN4 is 10% to 90% VIL VIH VIHy II Input low voltage Input high voltage Input voltage hysteresis (1) Input pull down current VIN = 5V, VS 6.5V -0.3 2 20 8 20 1 6 500 40 V V mV
A
Digital Outputs (ST1 to ST4) VSTL VSTH Status output voltage in low state (2) Status output voltage in high state 2) IST 40A IST -40A IST -120A RDIAGL RDIAGH ROUT + RDSON in low state ROUT + RDSON in high state 0 2.5 2 0.3 1.5 0.64 3.2 0.4 3.45 3.45 1.5 7.0 V V V k k
Power Outputs (Q1 to Q4) RDSON1,2 Static drain-source ON-resistance Q1 and Q2 (non-reg. channels) IQ = 1A; VS 9.5V Tj = 25C Tj = 125C(3) Tj = 150C(4) RDSON3,4 Static drain-source ON-resistance Q3 and Q4 (reg. channels) IQ = 1A; VS 9.5V Tj = 25C Tj = 125C 3) Tj = 150C 4) VF_250mA Forward voltage of free wheeling path D3, D4 @250mA VF_2.25A Forward voltage of free wheeling path D3, D4 @2.25A Rsens Sense resistor = (VF_2.25A-VF_250mA)/ 2A ID3/4 = -250mA ID3/4 = -2.25A 0.5 2.0 1 0.35 0.75 0.75 1.5 4.5 0.2 0.5 0.5

V V
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ELECTRICAL CHARACTERISTCS: (continued) (Vs = 4.8 to 18V; Tj = -40 to 150C unless otherwise specified)
Symbol VZ IPD IQlk Timing tON tOFF Output ON delay time Output OFF delay time channel IQ = 1A IQ = 1A
(5)
Parameter Z-diode clamping voltage Output pull down current Output leakage current
Test Condition IQ 100mA VEN = H, VIN = L VEN = L; VQ = 20V
Min. 45 10
Typ.
Max. 60 150 5
Unit V
A A
0 0
5 10 528
20 30
s s s
tOFFREG Output OFF delay time regulator tr tf tsf tlf tSCP tD tRE tDreg Output rise time Output fall time Short error detection filter time Long error detection filter time Short circuit switch-OFF delay time Status delay time Regulation error status delay time Output off status delay time
IQ = 1A IQ = 1A fCLK = 250kHz DC = 50%(5) fCLK = 250kHz DC = 50%(5)
(5) (5) (5)
0.5 0.5 4 16 4 896
1.5 1.5
8 8 8 32 30 1024
s s s s s
us ms
10 528
(reg. channels only)
(5)
(reg. channels only
s
Reg. Current Accuracy (reg. channels only) IQ3/Q4 IQ3/Q4 IREG Minimum current Maximum current Max. regulation deviation @ DC 10% - 90% DC = 10% DC = 90% 250mA < IQ3/Q4 < 400mA 400mA IQ3/Q4 800mA 800mA < IQ3/Q4 < 2.25A 5 200 2 250 2.25 300 2.5 10 6 10 mA A % % % mA
IQ3/Q4 Min. quant. step
Frequencies CLK frequency Input PWM frequency
(1) (2) (3) (4) (5)
crystal-controlled (reg. channels only)
250 2
kHz kHz
This parameter will not be tested but assured by design Short circuit between two digital outputs (one in high the other in low state) will lead to the defined result "LOW" Measured chip, bond wires not included Measured on Power SO-36 devices Digital filtered with external clock, only functional test
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1.0 1.1 Functional Description Overview
The L9347 is designed to drive inductive loads (relays, electromagnetic valves) in low side configuration. Integrated active Zener-clamp (for channel1 and 2) or free wheeling diodes (for channel 3 and 4) allow the recirculation of the inductive loads. All four channels are monitored with a status output. All wiring to the loads and supply pins of the device are controlled. The device is self-protected against short circuit at the outputs and overtemperature. For each channel one independent push-pull status output is used for a parallel diagnostic function. Channel 3 and 4 work as current regulator. A PWM signal on the input defines the target output current. The output current is controlled through the output PWM of the power stage. The regulator limits of 10% or 90% are detected and monitored with the status signal. The current is measured during recirculation phase of the load. A test mode compares the differences between the two regulators. This "drift" test compares the output PWM of the regulators. By this feature a drift of the load during lifetime can be detected. 1.2 Input Circuits
The INput, CLK, TEST and ENable inputs, are active high, consist of Schmidt triggers with hysteresis. All inputs are connected to pull-down current sources. 1.3 Output Stages (not regulated) Channel 1 and 2
The two power outputs (5A) consist of DMOS-power transistors with open drain output. The output stages are protected against short circuit. Via integrated Zener-clamp-diodes the overvoltage of the inductive loads due to recirculation are clamped to typ. 52V for fast shut off of the valves. Parallel to the DMOS transistors there are internal pull-down current sources. They are provided to assure an open load condition in the OFF-state. With EN=low this current source is switched off, but the open load comparator is still active. 1.4 Current-Regulator-Stages Channel 3 and 4 The current-regulator channels are designed to drive inductive loads. The target value of the current is given by the duty cycle (DC) of the 2kHz PWM input signal. The following figure shows the relation between the input PWM and the output current and the specified accuracy. Figure 3. Input PWM to output current range
2250 OUTPUT Current [mA]
+-10% 800
+- 6%
400
10%
250
10
INPUT PWM[%]
Cu rr e
nt p
re c
isi
on
90
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The ON period of the input signal is measured with a 1MHz clock, synchronized with the external 250kHz clock. For requested precision of the output current the ratio between the frequencies of the input signal and the external 250kHz clock has to be fixed according to the graph shown in Fig. Figure 4. Current accuracy according to the input and clock frequency ratio
5.6% 112.5 Regulator 125 0% switched off 132 fCLK / fIN
current accuracy -10%
The theoretical error is zero for fCLK / fIN = 125. If the period of the input signal is longer than 132 times the period of the clock the regulator is switched off. For a clock frequency lower than 100kHz the clock control will also disable the regulator. For high precision applications the clock frequency and the input frequency have to be correlated. The output current is measured during the recirculation of the load. The current sense resistor is in series to the free wheeling diode. If this recirculation path is interrupted the regulator stops immediately and the status output remains low for the rest of the input cycle. The output period is 64 times the clock period. With a clock frequency of 250kHz the output PWM frequency is 3.9kHz. The output PWM is synchronized with the first negative edge of the input signal. After that the output and the input are asynchronous. The first period is used to measure the current. This means the first turn-on of the power is 256s after the first negative edge of the input signal. As regulator a digital PI-regulator with the Transfer function for: KI: and KP: 0.96 for a sampling time of 256us is realised. To speed up the current settling time the regulator output is locked to 90% output PWM untill the target current value is reached. This happens alsowhen the target current value changes and the output PWM reaches 90% during the regulation. The status output gets low if the target current value is not reached within the regulation error delay time of tRE=10ms. The output PWM is than out of the regulation range from 10% to 90%. 1.5 Protective Circuits
0.126 -------------z-1
The outputs are protected against current overload, overtemperature, and power-GND-loss. The external clock is monitored by a clock watchdog. This clock watchdog detects a minimal frequency fCLK,min and wrong clock duty cycles. The allowed clock duty cycle range is 45% to 55%. The current-regulator stages are protected
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against recirculation errors, when D3 or D4 is not connected. All these error conditions shut off the power stage and invert the status output information. 1.6 Error Detection
The status outputs indicate the switching state under normal conditions (status LOW = OFF; status HIGH = ON). If an error occurs, the logic level of the status output is inverted, as listed in the diagnostic table below. All external errors, for example open load, are filtered internally. The following table shows the detected errors, the filter times and the detection mode (on/off).
ON State EN &IN = HIGH X OFF State EN &IN = LOW Filter time tsf X X X X X tlf tsf tsf tlf Reset done by EN & IN = "LOW" for TD or TDreg timer T D timer T D EN & IN = "LOW" for TD or TDreg in on: EN & IN = "LOW" for TD or TDreg in off: timer TD timer T D timer T D in on: EN & IN = "LOW" for TD or TDreg in off: timer TD in on: EN & IN = "LOW" for TD or TDreg in off: timer TD
Short circuit of the load Open load (under voltage detection) Open load (under current detection) Overtemperature Power-GND-loss
Signal-GND-loss Supply-VS-loss Clock control
X X X
X X X
tlf tlf no
Output voltage clamp active
X (regulated channels)
no
EN&IN=low means that at least one between enable and input is low. For the inputs IN=low means also no input PWM. For the regulator input period longer than TDreg and for the standard channel input period longer thanTD. A detected error is stored in an error register. The reset of this register is made with a timer TD. With this approach all errors are present at the status output at least for the time T D. All protection functions like short circuit of the output, overtemperature, clock failure or power-GND-loss in ON condition are stored into an internal "fail" register. The output is then shut off. The register must be reset with a low signal at the input. A "low signal" means that the input is low for a time longer than TD or TDReg for the reulated channel, otherwise it is interpreted as a PWM input signal and the register is left in set mode. Signal-GND-loss and VS-loss are detected in the active on mode, but they do not set the fail register. This type of error is only delayed with the standard timer tlf function. Open load is detected for all four channels in on- and off-state. Open load in off condition detects the voltage on the output pin. If this voltage is below 0.33 * VS the error register is set and delayed with TD. A sink current stage pull the output down to ground, with EN high. With EN low the output is floating in case of openload and the detection is not assured. In the ON state the load current is monitored by the non-regulated channels. If it drops below the specified threshold value IQU an open load is detected and the error register is set and delayed with T D. A regulated channel detects the open load in the on state with the current regulator error detection. If the output PWM reaches 90% for a time longer than t RE than an error occurs. This could happen when no load is connected, the resistivity of the load is too high or the supply voltage too low. The same error is shown if the regulator is not able to reduce the current in the load in the time tRE, so the output PWM falls below 10%. A clock failure (clock loss) is detected when the frequency becomes lower than fCLK,min. All status outputs are
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set on error and all power outputs are shut off. The status signals remain in their state until the clock signal is present again. A clock failure during power on of VCC is detected only on the regulated channels. The status outputs of the channel 1 and 2 are low in this case. 1.7 Drift Detection (regulated channels only)
The drift detection is used to compare the two regulated channels during regulation. This "Drift" test compares the output PWM of the regulators. The resistivity of the load influences the output PWM. The approximated formula for the output current below shows the dependency of the load resistor to the output PWM. In this formula the energy reduction during the recirculation is not taken into account. The real output PWM is higher. The testmode is enabled with IN,EN and TEST high. With an identical 2kHz PWM-Signal connected to the IN-inputs the output PWM must be in a range of +-14.3%. If the difference between the two on-times is more than 14.3% of the expected value an error is detected and monitored by the status outputs, in the same way as described above, but a drift error will not be registered and also not delayed with T D as other errors
VBAT IOUT = --------------------------- PWM RL + RON
Drift Definition: Drift = PWM(1+E) - PWM (1-E) = 2PWM E Drift * 4 < PWM (1+E) with E >14.3% a drift is detected E.. not correlated Error of the channels %PWM ... Corresponding ideal output PWM to a given input PWM A 7bit output-PWM-register is used for the comparison. The register with the lower value is subtracted from the higher one. This result is multiplied by four and compared with the higher value. 1.8 Other Test modes
The test pin is also used to test the regulated channels in the production. With a special sequence on this pin the power stages of the regulated channels can be controlled direct from the input. No status feedback of the regulated channels is given. The status output is clocked by the regulator logic. The output sequence is a indication of a proper logic functionality. The following table shows the functionality of this special test mode
EN 1 1 0 0 0 0 0 IN X 1 X X X 0 1 TEST X 1 OUT X on off off off off on STATUS X 1 test pattern test pattern test pattern test pattern test pattern Note disable test mode Drift mode test condition one test condition two test condition three test condition four test condition four
For more details about the test condition four see timing diagram.
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Diagnostic Table The status follows the input signal in normal operating conditions. If any error is detected the status is inverted.
Operating Condition Test Input TEST L L L L L L L L L L L L L L L L L L L L L L L L H H H H Enable Input ENA L L H H L L H H H H H -> L H H H H -> L H H H H -> L H L L H H L L H H Control Input non-reg./reg. IN L H/PWM L H/PWM L H/PWM L H/PWM H/PWM H/PWM X H/PWM -> L H/PWM H/PWM X H/PWM -> L PWM PWM X PWM -> L L H/PWM L H/PWM L H/PWM H/PWM H/PWM Power Output/ Current reg. Q OFF OFF OFF ON OFF OFF OFF ON OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF ON ON Status Output ST L L L H X X H L L L L L L L L L L L L L H H H L X X L H
Normal function
Open load or short to ground
Overload or short to supply Latched overload Reset latch Reset latch Overtemperature Latched overtemperature Reset latch Reset latch Recirculation error (reg.chn.) Latched error Reset latch Reset latch Clock failure (clock loss)
(1)
Drift Failure No failure
(2)
(1) during power on sequence only detected on channel 3 and 4 (see description). (2) This input combination is also used for an internal chip-test and must not be used.
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2.0 Timing Diagrams
2.1 Non Regulated Channels Figure 5. Output Slope, Resistive Load
VI VIH
VIL t VQ VS 85% V S 15% V S t
99AT0061
tON
tf
tOFF
tr
Figure 6. Overload Switch-OFF Delay
IQ IQO
IQU t tD VST tsf tSCP
t
00RS0001
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Figure 7. Normal Condition, Resistive Load, Pulsed Input Signal
VIN
VQ
IQ tD tD
IQU
VST
99AT0063
Figure 8. Current Overload
tD
Reset Fail register
VIN
VQ
Set Fail register
IQO
IQ tD
VST
99AT0064
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Figure 9. Diagnostic Status Output at Different OPEN Load Current Conditions
Under current condition followed by normal operation tD
VIN
VQ
IQ tD
IQU
VST
99AT0065
Open load condition in the case of pulsed input signal followed by normal operation tD
VIN
VQ
IQ tD
IQU
VST
99AT0066
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Figure 10. Pulsed Open Load Conditions (regulated and non-regulated channels)
VIN
VQ
0.33 x VS
IQ tlf tD tlf
VST
99AT0067
2.2 Regulated Channels (timing diagrams of diagnostic with 2kHz PWM input signal) Figure 11. Normal Condition, Inductive Load
500s
tDREG
VIN
VQ
Target Current IQ 256s 256s
VST
99AT0068
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Figure 12. Current Overload
500s tDREG
Reset Fail register
VIN
VQ IQO IQ tsf VST
Set fail registor
99AT0069
Figure 13. Recirculation Error
500s
tDREG
Reset Fail register
VIN
VQ
Set Fail register
target current
IQ
VST
99AT0070
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Figure 14. Current Regulation Error (e.g. as a result of voltage reduction)
500s
VIN
VQ
IQ
target current
PWM ratio = 90% tRE
VST
99AT0071
Figure 15. Overtemperature
Overtemperature Condition
500s
tDREG
Reset Fail register
VIN
VQ
Set Fail register
IQ
target current
VST
99AT0072
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Figure 16.
Test mode 4 VEN low
VTEST
VIN3/4
VQ3/4
99AT0073
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DIM. A a1 a2 a3 b c D (1) D1 E e e3 E1 (1) E2 E3 E4 G H h L N S
MIN. 0.10 0 0.22 0.23 15.80 9.40 13.90
mm TYP.
MAX. 3.60 0.30 3.30 0.10 0.38 0.32 16.00 9.80 14.50
MIN. 0.004 0 0.008 0.009 0.622 0.370 0.547
inch TYP.
MAX. 0.141 0.012 0.130 0.004 0.015 0.012 0.630 0.385 0.570
OUTLINE AND MECHANICAL DATA
0.65 11.05 10.90 5.80 2.90 0 15.50 0.80 11.10 0.429 2.90 6.20 0.228 3.20 0.114 0.10 0 15.90 0.610 1.10 1.10 0.031 10(max.) 8 (max.)
0.0256 0.435 0.437 0.114 0.244 0.126 0.004 0.626 0.043 0.043
PowerSO36
(1): "D" and "E1" do not include mold flash or protrusions - Mold flash or protrusions shall not exceed 0.15mm (0.006 inch) - Critical dimensions are "a3", "E" and "G".
N
N a2 A DETAIL A e3 H lead e A a1 E DETAIL A
c DETAIL B
D a3
36 19
slug BOTTOM VIEW E3
B E2 E1 DETAIL B
0.35 Gage Plane
D1
1
1
8
-C-
S h x 45 b
0.12
M
L
SEATING PLANE G C
AB
PSO36MEC
(COPLANARITY)
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (R) 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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